Modular multilevel converters (MMCs) are made up of many submodules (SMs) connected in series. In order to avoid semiconductor over-voltages, SM capacitors should be kept within strict voltage limits. The capacitor balancing controller (CBC) is used to sort SM capacitor voltages prior to modulation. This paper investigates the variation in sorting complexity at steady state and transient conditions for a brute-force and past-position methodology based on the bubble sort algorithm. A focus is placed on the potential for ‘worst-case’ sorting, requiring increased computational effort. This paper forms part of on-going research to analyze the hardware constraints on MMCs with very large numbers of SMs. Simulation results based on a PSCAD/EMTDC detailed equivalent model are used for analysis and conclusions.
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